PCI Enumeration Troubleshooting

A firmware engineer playbook for PCIe devices that disappear, show wrong resources, or fail driver binding after enumeration.

2 min read
Shell & Firmware Tools cover

A PCIe endpoint is missing.

The fastest mistake is to jump straight into driver code.

PCI enumeration failures are often decided much earlier: reset, clock, power, lane routing, root port policy, bridge windows, or firmware setup options.

01 Hardware

Power / reset / clock

Check rails, PERST#, reference clock, strap pins, and board routing.

02 Link

PCIe link training

Check whether the root port and endpoint train to a valid link state.

03 Firmware

Root port policy

Check setup options, lane bifurcation, hotplug, ASPM, and port enable policy.

04 Enumeration

BDF appears

Use lspci to verify bus/device/function and Vendor ID / Device ID.

05 Resources

BAR and bridge windows

Check BAR assignment, Command Register, and upstream bridge resource windows.

06 Driver

OS binding

Only after enumeration is valid, debug driver match, ACPI companion, interrupt, and power state.

PCIe missing device debug path

Symptom map

Item Value Note
No device in lspci Enumeration failure Start with link, reset, power, clock, root port enable, or bus numbering.
Vendor ID is 0xFFFF No config response Often link/device response issue rather than driver issue.
Device appears, no driver Binding failure Check Vendor ID, Device ID, class code, ACPI companion, and driver support.
BAR unassigned Resource allocation issue Check bridge windows, MMIO aperture, Above 4G decoding, and firmware resource policy.
Driver loads, device dead Runtime failure Check interrupts, DMA, power state, reset GPIO, _DSM, or firmware configuration.

Debug Diary: M.2 device missing on one SKU

A common real case:

Same BIOS branch
Different board SKU
NVMe missing only on SKU-B

Useful checks:

Is the root port enabled for SKU-B?
Is lane mux configured differently?
Is CLKREQ# wired?
Is PERST# controlled by GPIO or fixed logic?
Does setup hide a port enable option?
Does lspci show the upstream root port but not endpoint?

This is why PCI debug belongs in a firmware Knowledge Base, not only a Linux command guide.

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